1. Field of the Invention
The present invention relates to a multiple determination apparatus used in a circuit for detecting an error of a digital signal in a packet communication system or the like.
2. Description of the Related Art
For example, in moving picture communications, moving picture data is divided into 188-byte moving picture expert image coding group phase 2 (MPEG2) transport stream packets, and is stored in asynchronous transfer mode (ATM) packets which are transmitted. In a receiving side that receives such ATM packets, it is required that a byte length of each ATM packet is a multiple of 188. For this purpose, a multiple determination apparatus is provided.
A first prior art multiple determination apparatus includes a shift circuit for shifting a dividend and a downcounter for counting the bit length of the dividend in addition to an operational circuit formed by selector circuits, a memory circuit and a subtracter circuit. This will be explained later in detail.
Therefore, in the first prior art multiple determination apparatus, since the shift register and the downcounter are required, the hardware of the apparatus is increased, which increases the manufacturing cost.
Since the selector circuit connected to the subtracter circuit is operated by the borrow signal of the subtracter circuit, it is impossible to increase the operation speed of the selector circuit, so that the operation speed of the apparatus cannot be increased. Further, since the number of clock signals is as many equal to the effective bit length of the dividend plus 1, the entire operation time is increased, which further decreases the operation speed.
In a second prior art multiple determination apparatus (see JP-A-8-202534), the shift circuit and the downcounter of the first prior art multiple determination apparatus are not provided, which decreases the hardware. This will be also explained later in detail.
In the second prior art multiple determination apparatus, however, since the number of clock signals is remarkably increased, the entire operation time is remarkably increased, which decreases the operation speed.
In a third prior art multiple determination apparatus, a table showing relationships between all possible dividends and data indicating whether or not a multiple of a certain divisor is provided, thus remarkably increasing the operation speed.
In the third prior art multiple determination apparatus, however, a memory for storing such a table is remarkably enlarged. For example, if each dividend is constructed by n bits, a 2.sup.n bits capacity memory is required. That is, if n=16, 2.sup.16 =65000 bits. Thus, the hardware is increased.